Raspberry Pi Zero as a Second Processor anyone?

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fordp
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Wed Mar 09, 2016 11:15 pm

OK I think we have the MOVX and MOVZ wrong.

I think in all cases the input size is set by the two i bits (bit 8 and bit 9) and the output operand size is hard coded. There are patterns that would copy but do nothing special.

Input 16 bits Output 16 bits would work like a normal MOV but I think is in there.

It is written like it is as when writing to a 16 bit value the only conversion would be from 8 bits.

When writing to 32 bits there would be two conversions and one plan 32 bit copy.

So there are 12 variants in total 6 documented useful ones and 6 not so useful undocumented ones.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Wed Mar 09, 2016 11:51 pm

fordp wrote:OK I think we have the MOVX and MOVZ wrong.

I've looked at the code, and at all the documentation, and I can't see us doing anything that's incorrect.

Can you give a specific example that we are messing up?

Or are you just saying there is a simpler way to code this?

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 7:57 am

I do not think we have it coded like I think it is implemented in the chip and there are 6 undocumented instructions.

The way we have it coded now it would not properly implement four of those instructions and if they are found in the wild, say in Panos it would fail.

The hint for this came when I was trying to write the code to show the instruction names.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 10:46 am

Hi Guys,

Some progress on the FPGA front.

I've now got a way of capturing a trace of Panos booting on the Matchbox LX9.

I've added a state machine to the design that can control the 32016 clock. After each program counter change, it stops the 32016 clock, sends the new program counter out of the test connector 6 bits at a time with a clock (so 8 cycles in total), then re-starts the 32016 clock. It only does this if the address is < 0xF00000, so we don't interfere with the data transfers, etc, in Pandora.

This version is checked in to a branch:
https://github.com/hoglet67/CoPro6502/b ... 2016.v#L67

I'm then able to capture the trace with a USBee SX logic analyzer. This can capture 300M samples @ 12MHz, which is 25 seconds worth - enough time for Panos to boot.

The trace is saved as a binary file, and then a small C program looks for clock transitions on bit 7, and re-assembles the 6-bit chunks back into 24-bit PC values:
https://github.com/hoglet67/PiTubeClien ... /process.c

The final result looks like:

Code: Select all

&000400
&000403
&000406
&000FCE
&000FD1
&000FE8
&000FEB
&000FF1
&000FF4
&000FF8
&000FFB
&001200
&001202
&001204
&00120E
&001212
&001215
...

Now comes the interesting bit....

Comparing it against the Pi trace, they are identical for 274490 instructions, then they start to diverge.

But I think this first point of divergence is a false positive, because instruction 274399 is a system call to read the system clock (using OSWORD).

Interestingly, if I compare two separate Pi Traces, I see differences in register values between runs at about this point as well.

I think we need to somehow eliminate this variability.

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 11:59 am

Amazing =D> =D> =D> =D>

A hack on the BBC trapping the time call and returning a fixed value will help?
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 12:10 pm

Beware of interruptible instructions, they may be implemented differently on the LX9 and the soft-core.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby danielj » Thu Mar 10, 2016 12:11 pm

Can I just say how much I'm enjoying this thread? :D

-> Dave, can I use this to try and work out why the 32016 is hanging on loading Panos on that Master?

d.

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby jgharston » Thu Mar 10, 2016 12:18 pm

hoglet wrote:But I think this first point of divergence is a false positive, because instruction 274399 is a system call to read the system clock (using OSWORD).
Interestingly, if I compare two separate Pi Traces, I see differences in register values between runs at about this point as well.
I think we need to somehow eliminate this variability.

Would the latency be small enough for TIME=0:*panos to work?

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 12:45 pm

jgharston wrote:
hoglet wrote:But I think this first point of divergence is a false positive, because instruction 274399 is a system call to read the system clock (using OSWORD).
Interestingly, if I compare two separate Pi Traces, I see differences in register values between runs at about this point as well.
I think we need to somehow eliminate this variability.

Would the latency be small enough for TIME=0:*panos to work?

Actually, the execution speed is very different:
- On the FPGA it's running close to real time.
- On the Pi, because the instruction trace is coming out of the serial port, it's about 100x slower than real time.

So any initial latency is probably irrelevant.

I'm going to try another run setting TIME=0 at the start...

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 1:34 pm

I can see a bug in my live trace of decoding displacements and other data coming after the basic instruction.

I will try and fix it sometime today. In the meantime you may have to use an older version :(
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 6:30 pm

danielj wrote:Can I just say how much I'm enjoying this thread? :D

You're welcome :D
danielj wrote:-> Dave, can I use this to try and work out why the 32016 is hanging on loading Panos on that Master?

It would certainly be possible to generate a 32016 PC address trace from the bad Master, and compare it against the good one.

Although as I'm now finding, just knowing where two traces diverge doesn't always help you to understand why!

I think once we get the Pi 32016 Emulation working, that may be a better way to go.

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 7:19 pm

Hi Guys,
fordp wrote:I can see a bug in my live trace of decoding displacements and other data coming after the basic instruction.

I will try and fix it sometime today. In the meantime you may have to use an older version :(

I've done another run today with the latest code, this time trying to eliminate the system time variation by setting TIME=0 at the start of the run. That actually seems to have been successful. I've attached it here in case anyone else want to look:
v4.zip
(1.38 MiB) Downloaded 17 times

The FPGA and Pi instruction traces now diverge about 60,000 instructions later, and this time I don't think it's time based.

I've done two separate runs on the Pi - one with just instruction logging, the other with registers as well (which takes hours). These are 100% identical, so at least we know there no random variation creeping in.

Anyway, here's the first couple of real differences:

Code: Select all

337755a337756,337757
> &0041BE
> &0041C0
337760,337763c337762,337766
< &0041DE
< &0041E1
< &0041E3
< &0041E9
---
> &0041D0
> &0041D2
> &0041D4
> &0041DA
> &0041DC

Here's the code leading up to first difference:

Code: Select all

&0042E2 [00820432] F1 RXP  x'4
&00431A [85E705D7] F4 MOVD R0,TOS
&00431C [000C85E7] F4 ADDRD 0(12(FP)),TOS
&004320 [00921A22] F1 CXP  x'1A
&00418B [1724F082] F1 ENTER [R4,R5,R6,R7] x'24
&00418E [1F10C117] F4 MOVD 16(FP),R4
&004191 [810A201F] F2 CMPQD 0,R4
&004193 [1718810A] F0 BEQ &0042AB
&004196 [A02B2017] F4 MOVD R4,R0
&004198 [0000A02B] F4 ANDD x'3,R0
&00419E [1F7C0617] F4 MOVD R0,-4(FP)
&0041A1 [080A001F] F2 CMPQD 0,R0
&0041A3 [0A5F080A] F0 BEQ &0041AB
&0041AB [1770C05F] F2 MOVQD 0,-16(FP)
&0041AE [6414D617] F4 MOVD 20(SB),-28(FP)
&0041B2 [046481D7] F4 MOVD 4(-28(FP)),R7
&0041B6 [87007997] F4 MOVD 0(R7),R6

And the first point of divergence:

Code: Select all

&0041B9 [0A08D187] F4 CMPD 8(SB),R6
&0041BC [3987080A] F0 BEQ &0041C4        ;; on the FPGA, this branch is taken skipping the next two instructions
&0041BE [04AA3987] F4 CMPD R7,R6
&0041C0 [122204AA] F0 BLO &0041C4
&0041C4 [0400A3F4] F4 TBITB x'0,4(R7)    ;; traces re-converge here
&0041C8 [8734808A] F0 BFS &0041FC
&0041CB [0A08D187] F4 CMPD 8(SB),R6
&0041CE [3017100A] F0 BEQ &0041DE        ;; on the FPGA, this branch is taken, changing the next five instructions
&0041D0 [38233017] F4 MOVD R6,R0
&0041D2 [A0233823] F4 SUBD R7,R0
&0041D4 [0000A023] F4 SUBD x'8,R0
&0041DA [0FEA0157] F4 MOVD R0,R5
&0041DC [D0170FEA] F0 BR &0041EB
&0041EB [074A2147] F4 CMPD R4,R5         ;;  traces re-converge here

Jonathan's disassembly might also be useful to fill in some of the gaps:
http://mdfs.net/Software/32000/PanOS14/PanosData.lst

I'm open to ideas as to how best to proceed now. It's really not obvious what's causing the difference.

I might try to include write addresses in the FPGA trace, so we can see in the Pi if a write is going astray.

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 7:57 pm

I have just posted hopefully a fix for the bug earlier.

I now decode pretty much all the instructions in the Test Suite.

The post run disassembly is should be close to being ready to feed back in to an assembler! I do not add labels yet that will be some fun for another day.

Here is the transition from run to disassembly on the test suite:

Code: Select all

&001C6C [D000A1D5] F4 MOVW x'D017A0,R7
*** TEST = 208
&001C70 [0000A017] F4 MOVD x'A,R0
&001C76 [D721D867] F4 ADDRD * + 33,R1
&001C79 [A37C08D7] F4 MOVD R1,R3
&001C7B [0E20A37C] F3 BISPSRB x'200E8C00
&001C7E [8A008C0E] F5 SKPST
&001C81 [18632A8A] F0 BFS &001C64
&001C83 [A0471863] F4 SUBD R3,R1
&001C85 [0000A047] F4 CMPD x'A,R1
&001C8B [001F201A] F0 BNE &001CAA
&001C8D [1C1A001F] F2 CMPQD 0,R0
&001C8F [A57D1C1A] F0 BNE &001C8C
&001C91 [0001A57D] F3 ADJSPW x'100EA0E
&001C95 [7C000EEA] F0 BR &001C95
&001CA3 [DDE73817] F4 MOVD R7,R0
&001CA5 [6CA3DDE7] F4 ADDRD * + -7316,TOS
DisassembleUsingITrace(000000, 010000)
#000001: &000000 [000D20EA] F0 BR &000020
.byte 13,0,70,97,105,108,99,111,100,101,32,58,32,18,0,32,84,101,115,116,115,32,99,111,114,114,101,99,116,46
#000001: &000020 [A4EF385F] F2 MOVQD 0,R7
#000001: &000022 [0100A4EF] F2 LPRD SP,x'10000
#000001: &000028 [A01738DD] F2 MOVQW 1,R7
#000001: &00002A [FFFFA017] F4 MOVD x'FFFFFFAA,R0
#000001: &000030 [07CCA028] F4 ANDB x'CC,R0
#000001: &000033 [FFFFA007] F4 CMPD x'FFFFFF88,R0
#000001: &000039 [5D799C1A] F0 BNE &001CB2
#000001: &00003C [A017395D] F2 MOVQW 2,R7
#000001: &00003E [FFFFA017] F4 MOVD x'FFFF5555,R0
#000001: &000044 [3333A029] F4 ANDW x'3333,R0
#000001: &000048 [FFFFA007] F4 CMPD x'FFFF1111,R0
#000001: &00004E [DD649C1A] F0 BNE &001CB2


The top is the end of the run then it switches to listing the taken code with bits in between shown as data. The count on the left is the number of times it visited that PC! So bits of code are used 32 times on the test (some 31 too for some reason).
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 8:05 pm

1) Add the ability to turn on tracing on both platforms at a particular PC.
2) Can you trace out the two operands (inputs) ?

Compare and work out which is different.

"SB offset" looks favourite but who knows.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 8:18 pm

fordp wrote:"SB offset" looks favourite but who knows.

"SB offset" is now really just one line of code:

Code: Select all

         case SbRelative:
            genaddr[c] = getdisp() + sb;
            break;
 

The code is now so clean and minimal, it's hard to see where any remaining bugs might be hiding :lol:

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby jgharston » Thu Mar 10, 2016 8:19 pm

hoglet wrote:I've done another run today with the latest code, this time trying to eliminate the system time variation by setting TIME=0 at the start of the run. That actually seems to have been successful. I've attached it here in case anyone else want to look:
v4.zip

That's useful. It appears to show that panos enters pandata at &210C, so I have a base to start commenting from.

(I'm used to debugging with a running register dump, eg
0000210E ADDB R0,R0 R0=00002000 R1=12340292 R3=etc SB=04C0 MOD=0018 PSW=NV---Z--
but that would generate HUGE amounts of data. I regularly crashed my A440 with Disk Full errors when first getting Z80Tube working)

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 8:30 pm

jgharston wrote:(I'm used to debugging with a running register dump, eg
0000210E ADDB R0,R0 R0=00002000 R1=12340292 R3=etc SB=04C0 MOD=0018 PSW=NV---Z--
but that would generate HUGE amounts of data. I regularly crashed my A440 with Disk Full errors when first getting Z80Tube working)

Code: Select all

Entering Panos
&000400 [D708DDD7] F4 MOVD * + 8,TOS
R0=00000050 R1=00000001 R2=00000000 R3=00000000
R4=00000001 R5=00000000 R6=00000000 R7=00000000
PC=00000403 SB=8284130D SP=001FF9B4 TRAP=00000000
FP=00000000 INTBASE=001FFE64 PSR=0B84 MOD=0100

&000403 [3209DDD7] F4 MOVD * + 9,TOS
R0=00000050 R1=00000001 R2=00000000 R3=00000000
R4=00000001 R5=00000000 R6=00000000 R7=00000000
PC=00000406 SB=8284130D SP=001FF9B0 TRAP=00000000
FP=00000000 INTBASE=001FFE64 PSR=0B84 MOD=0100

&000406 [04100032] F1 RXP  x'0
R0=00000050 R1=00000001 R2=00000000 R3=00000000
R4=00000001 R5=00000000 R6=00000000 R7=00000000
PC=00000FCE SB=000012D0 SP=001FF9B8 TRAP=00000000
FP=00000000 INTBASE=001FFE64 PSR=0B84 MOD=0410

&000FCE [0200BEA7] F4 ADDRD TOS,0(SB)
R0=00000050 R1=00000001 R2=00000000 R3=00000000
R4=00000001 R5=00000000 R6=00000000 R7=00000000
PC=00000FD1 SB=000012D0 SP=001FF9B8 TRAP=00000000
FP=00000000 INTBASE=001FFE64 PSR=0B84 MOD=0410

Do you want it? It's over 5MB compressed / 140MB uncompressed so I can't upload here. I could email it to you.

Or wait until tomorrow when I run another one with Ford's bug-free live disassembly?

(BTW, it's amazing how well emacs deals with 140MB text files!!)

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby jgharston » Thu Mar 10, 2016 9:03 pm

hoglet wrote:Do you want it? It's over 5MB compressed / 140MB uncompressed so I can't upload here. I could email it to you.

Hold on, let me just clear a load of crap from my mailbox. ;)

Or wait until tomorrow when I run another one with Ford's bug-free live disassembly?

Well, I'm working in Newcastle tomorrow, then it's my half-brother's wedding at the weekend, so I wouldn't be doing much with it until next week, so I can wait for a later run.

(BTW, it's amazing how well emacs deals with 140MB text files!!)

I use metapad on Windows which, while is struggles to actually "load" a humungous file, once it's got its claws into it it happilies plays with it.

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 9:28 pm

Question does Udo's core implement the debug features. I started adding it to the soft-core. If it does you could add a UART (say 6850) and we could write a small debugger?
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Thu Mar 10, 2016 9:52 pm

fordp wrote:Question does Udo's core implement the debug features. I started adding it to the soft-core. If it does you could add a UART (say 6850) and we could write a small debugger?

Well, it certainly includes the debug registers:
https://github.com/hoglet67/CoPro6502/b ... ERS.v#L121

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 10:26 pm

Well somebody who could write assembler could have fun with that. It could be tested on the Soft-core first. I would be happy to implement the debug module emulation.

I am still crap at assembler however!

I was thinking we need to be able to set the one and only breakpoint. When it hits that we need one command to start with "S" for single step.

You would set the breakpoint before loading Panos.

The monitor program would dump the registers out to the serial port after every step.

That would be a start.

It would also be a great way to test the exception handling of the soft-core.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Thu Mar 10, 2016 11:16 pm

jgharston wrote:
hoglet wrote:I've done another run today with the latest code, this time trying to eliminate the system time variation by setting TIME=0 at the start of the run. That actually seems to have been successful. I've attached it here in case anyone else want to look:
v4.zip

That's useful. It appears to show that panos enters pandata at &210C, so I have a base to start commenting from.

(I'm used to debugging with a running register dump, eg
0000210E ADDB R0,R0 R0=00002000 R1=12340292 R3=etc SB=04C0 MOD=0018 PSW=NV---Z--
but that would generate HUGE amounts of data. I regularly crashed my A440 with Disk Full errors when first getting Z80Tube working)


00F0017E 5C A8 C0 F9 00 00 \(@y.. MOVQB +0,@&00F90000 "This line pages out the Panos ROM from taking up all the address space"
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Fri Mar 11, 2016 7:43 am

Live trace is still broken with a new bug but it should be fixed in a few minutes ;)

EDIT: One bug squashed (branch locations wrong) but I think there is another in there. The code is in state of flux ahead of merging soft-core, live trace and disassembly with too many bodges to be reliable tight now :(

EDIT2: I think it may be better than I feared and I am maybe I am just not decoding some bit instructions properly.
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Fri Mar 11, 2016 10:23 am

fordp wrote:EDIT: One bug squashed (branch locations wrong) but I think there is another in there. The code is in state of flux ahead of merging soft-core, live trace and disassembly with too many bodges to be reliable tight now :(

EDIT2: I think it may be better than I feared and I am maybe I am just not decoding some bit instructions properly.

I take it these bugs all refers to the disassembly, rather the soft core itself?

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Fri Mar 11, 2016 11:37 am

Indeed Dave, I have been good and left 32016.c pretty much untouched.

I think I will manage to hold off on yet another rework until after Panos works, I need a test suite as complex as Panos to prove I have not broken anything I think with the changes I am planning, which are of course yet more simplification making the soft-core even closer to the real chip.

What did you think to my idea of using the built in debug features of the NS32xxx core?

It would be useful long after Panos boots. If we add a serial port it would allow hardware debugging to be added to other cores :D
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Fri Mar 11, 2016 11:49 am

I have just pushed a couple of warnings to flag if the missing instruction are encountered!
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Fri Mar 11, 2016 11:49 am

fordp wrote:What did you think to my idea of using the built in debug features of the NS32xxx core?

I sounds like it should be useful, but if I had it today I'm not sure exactly how I would use it to track down this bug.

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Fri Mar 11, 2016 1:17 pm

hoglet wrote:
fordp wrote:What did you think to my idea of using the built in debug features of the NS32xxx core?

I sounds like it should be useful, but if I had it today I'm not sure exactly how I would use it to track down this bug.

Dave

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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby hoglet » Fri Mar 11, 2016 1:40 pm

fordp wrote:
hoglet wrote:
fordp wrote:What did you think to my idea of using the built in debug features of the NS32xxx core?

I sounds like it should be useful, but if I had it today I'm not sure exactly how I would use it to track down this bug.

Dave

As the robot from short circuit would day more data. If you knew what the data that was being compared then there would be a clue.

More data is certainly good!

I'm working at the moment on trying to extend the FPGA logging to include a trace of write addresses and sizes, and maybe later add data.

Code: Select all

PC &000400
PC &000403
WD &1FF9B0
PC &000406
PC &000FCE
PC &000FD1
WD &0012D0
PC &000FE8
WD &1FF9B4
PC &000FEB
PC &000FF1
PC &000FF4
WD &0012D8
PC &000FF8
PC &000FFB
PC &001200
WD &1FF9AC
PC &001202
PC &001204
PC &00120E
WD &1FF9A4
PC &001212
PC &001215
PC &001217
WD &1FF9A0
PC &00121A
PC &00121C
PC &001220
PC &001224
WD &1FFDB8
WD &1FFDB4

Comparing this is going to be more difficult, because the way the FPGA and Pi handle un-aligned writes is different.

For example, a 32-bit write to address &001003 on the FPGA would be seen as two consecutive 32-bit writes:
- one with a byte enable mask of 1000
- the other with a byte enable mask of 0111

To be able to do a sensible comparison, I might have to re-work mem32016.c to work in the same way. Or reduce everything down to the lowest common denominator of byte writes.

Dave

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fordp
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Re: Raspberry Pi Zero as a Second Processor anyone?

Postby fordp » Fri Mar 11, 2016 4:15 pm

The Pi can be made to match the way the FPGA writes the data pretty easy. We must not forget about the pushing and popping uses different code however. A few hack and it can all go through the same methods. We can calculate what FPGA would have written and log accordingly.

Simulating the reading RAM would be MUCH harder however.
FordP (Simon Ellwood)
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