bbc master RDY

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dominicbeesley
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bbc master RDY

Postby dominicbeesley » Mon Feb 12, 2018 9:57 pm

I notice that the Master uses the 65c12's RDY line, and is connected to the PBC(IC21) and the IOC(IC15). Not having access to my Master at the moment I can't have a poke to see what this is used for - is it to do the 1MHzE cycle stretching or is it something more fancy?

D

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hoglet
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Re: bbc master RDY

Postby hoglet » Mon Feb 12, 2018 10:05 pm

dominicbeesley wrote:I notice that the Master uses the 65c12's RDY line, and is connected to the PBC(IC21) and the IOC(IC15). Not having access to my Master at the moment I can't have a poke to see what this is used for - is it to do the 1MHzE cycle stretching or is it something more fancy?

Yes, instead of stretching the 2MHz clock, the Master uses RDY to insert one or two wait states on access to certain I/O locations:
- &FC00-&FCFF
- &FD00-&FDFF
- &FE00-&FE1F
- &FE40-&FE7F
- &FE80-&FE9F
- &FEC0-&FEDF

I don't think it is used for anything else.

You can see an example here:
sigrok6.png

Dave

dominicbeesley
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Re: bbc master RDY

Postby dominicbeesley » Tue Feb 13, 2018 12:56 am

Thanks for that Dave, as I suspected but good to get confirmation.

That pulseview display looks brilliant! I need to get that working here...is it a plugin you've made?

D

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hoglet
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Re: bbc master RDY

Postby hoglet » Tue Feb 13, 2018 7:38 am

dominicbeesley wrote:That pulseview display looks brilliant! I need to get that working here...is it a plugin you've made?

The 6502 bit is indeed a plugin I wrote:
https://github.com/hoglet67/libsigrokde ... rs/mos6502

I switched development from a python plugin to a standalone C version for performance reasons (100x faster), and because sigrok is not geared up for working with very long captures. For example, there is no search capability in sigrok. So the C version is more functional, but the python plugin does work.

Dave