Looks interesting Alan - certainly the drop-in replacement is appealing but even so, it's still not a genuine solid gold SID
I wrote:I do solemnly swear that one evening next week I will post the schematics.
True to my word then…..
For a quick look, here’s a jpeg of the circuit diagram for the prototype BeebSID as already built and I’ve also attached a high-res TIFF image for better detail. Since it’s a relatively simple project, I think I might as well offer some background waffle as a learning exercise for anyone new to this stuff and you never know, it might also lead to further innovations in from the STH community
If you’re not into hardware (or only vaguely) then I’m sure this looks very impressive but in truth it’s just about as simple as a 1MHz bus peripheral device can get! When Tom asked for a concept proving unit and since I was struggling for time (as always), my personal remit was to build a prototype unit that would work perfectly but use as few chips as possible. I obviously had to have a SID chip, I wanted to have a minimum ‘clean-up’ circuit (see next) and any remaining chip(s) would attend to the necessary address one-meg bus decoding.
The 1MHz bus ‘clean-up’ circuit is well documented (e.g. AUG) and tackles a slight Acorn design hiccup in the ‘NOT PAGE $FC’ (NPGFC) select signal whereby glitches (unwanted very short duration pulses) can and will appear on NPGFC. This signal is used to automatically pre-select a memory mapped hardware page of 255 addresses (also known as ‘FRED’) and is used in conjunction with the lower 8 address lines (A0-A7) to ‘map’ chips and their registers onto the bus. Some devices won’t be affected by these very narrow glitches but the single chip fix is adequate for virtually all other devices including SID. Three of the four NOR logic gates in IC1 (LS02) use both NPGFC and the 1MHz bus clock (1MHzE) to provide a (virtually) clean NPGFC and any one-meg bus peripheral should have at least this circuit. The remaining gate in IC1 is simply used as an inverter because my design requires an active high select and NPGFC is active low.
The last design job is to pick an address or range of addresses at which your peripheral will reside within FRED. For speed (my speed!) and low chip count, I picked a base address for SID of $FCE0 and since the chip has 29 registers (addressable for 32 but 3 are unused) the last register appears at $FCFC. I picked $FCE0-$FCFC because (a) it is recorded as unused in the Acorn documentation and (b) because I knew I would be able to achieve the hardware address decoding with just one more chip, IC2 which is an 8 input Nand gate.
Now, digressing for a moment, there is absolutely no problem in my choice of address space except that there is always the possibility that someone else might at the same time be designing a different peripheral and if we both happen to pick the same addresses then our two devices cannot both be used simultaneously on the bus. What are the chances of that happening I hear you say…
Well, unless I’m very much mistaken, Mark (retroclinic
) has picked $FCF8 onwards for DataCentre and hence we have a 5 byte overlap or cock-up to give it the correct name
Given this, and despite the fact that Tom was already demo-ing BeebSID before DataCentre hit the streets
, I think I have no choice but to recommend, nay insist, that the above circuit is changed to locate BeebSID at a different base address within FRED – probably anywhere after/including $FC50 is safe unless someone knows different?
Other random thoughts and in no particular order…..Buffering and pass-through
: The prototype does not include any buffering and if BeebSID is all alone on the bus then this is fine. However, if we are thinking ahead (cue Arcadian
) then ideally every device would include full buffering. For example, I have used three hard-wired copies of the 1MHzE clock and I would at least rather see that signal buffered to support the fan-out. There should also be a 1MHz Bus pass-through expansion connector on each peripheral to allow daisy-chaining of multiple devices.Power
: The SID chip uses +5v and, irritatingly, +9v which is why there is a 7809 on-board. I powered the prototype from the Beeb disc drive power connector but this may cause some people problems so perhaps we need to agree some common standard for 1MHz bus power pick-up? Incidentally, if the +12v to the 7809 wasn’t already from a fully smoothed supply I would change the 7809 local capacitor arrangement. The 1k resistor is just a dummy load to make sure the regulator does regulate because I didn’t know how much current SID draws.
Perhaps three AA’s and a 9v PP3 would be a viable option for BeebSID?Filter caps
: These are 6800pf (the SID ‘default’) and work fine on the prototype but I understand that these may need to be varied to get the best audio performance from a given SID chip. Tom – could you expand on this please…Audio out
: I fitted a long flying lead with a Phono Plug for use with an external audio amp and speakers but I also connected the output to the 1MHz Bus ‘Analog In’ on Pin 16 which allows BeebSID to play through the Beeb’s internal amp and speaker. This would probably be better through a switch and Tom has commented that it doesn’t work on all machines. I think on the Master there are links in this area so Tom’s comments could be something to do with those?
If you have the skills (or know someone who has) then a fully working BeebSID can be built from the circuit above. However, I’d like to think that this initial post will promote discussion and that we can make this into a team effort with an ultimate aim of somebody producing PCB’s to allow easy construction and a common build standard. So please feel free to ask questions and make comments (no shaky fingers Mark) and let's see if we really can make a community project a goer