Fixing a Superbrain up

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jonb
Posts: 1689
Joined: Sat May 21, 2011 12:42 pm
Location: South Coast of England

Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 6:22 pm

Testing the 8255. The ROM does a sequence of outputs to its registers in the first few lines of code the ones I am interested in are:

Code: Select all

OUT 6B,08 - PPICW Control word port
Bit   Value   Meaning
0   0   PPIC lower half = OUTPUT
1   0   PPIB = OUTPUT
2   0   Mode = 0
3   1   PPIC upper half = INPUT
4   0   PPIA = OUTPUT
5,6   00   Mode select = 00
7   0   Mode set = SET

OUT 6A,B2 - PPIC port
Bit   Value   Meaning
0   0   RAM addressing = NORMAL
1   1   Character blanking = ON
2   0   RAM Bank 0 = ENABLE (CPU1 access to EPROM Disabled)
3   0   CPU2 = NORMAL (i.e., not in RESET)
4   1   RAM Bank 2 = ENABLE
5   1   CPU2 BUS REQUEST = ENABLE
6   0   Bell = OFF
7   0   Keyboard encoder = NORMAL


Looking at this, I think PPICW's settings aren't good for my tests as they set PPIC upper half to INPUT. So, I have tried OUT 6B,0 so that PPIC is all output, followed by OUT 6A,B2 and my memory map looks like this

Code: Select all

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
                                RRRRRRRRRRRRRRRR
                                WWWWWWWWWWWWWWWW
                                2222222222222222
                                0123456789ABCDEF


That is, only Bank 2 is visible (and the ROM is plugged in, but there is no RAM in Bank 0).

If I then try and enable the ROM access with OUT 6A,B6 I get the same memory map. I can see the ROM (list it using the ICE's disassembler) but as before, each subsequent read gives different results.

The other thing is that there is no signal on PC6 and PC7 according to my logic probe. Not worried right now as they control the Bell and Keyboard controller!

jonb
Posts: 1689
Joined: Sat May 21, 2011 12:42 pm
Location: South Coast of England

Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 6:50 pm

More fun with the 8255. Manual says control word is 82h, and I found that if I do OUT 6B,82, I get full control of port C as output, which is what I want. I tried this, then OUT 6A, 0 and probed the port - all lines low. Then OUT 6A,FF and probe again - all lines high. Plus, the beeper is on (goes back off after OUT 6A, 0). Perfect.

So naturally, I attempt to access the ROM again with OUT 6A,B6. No dice. Perhaps I can refit Bank 0 and get it going with OUT 6A,B2?

..no, it is showing as RAM but intermittent. So out with the ROM and data bus transceiver, and try again.

..no, it is showing as RAM, again intermittently. Interestingly, when I enable ROM it looks like ROM stuck at FF (with transceiver and ROM removed).

Now I have proper control of its inputs, I need to trace the paging logic (yet again).

jonb
Posts: 1689
Joined: Sat May 21, 2011 12:42 pm
Location: South Coast of England

Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 7:09 pm

Just thinking, maybe there is a timing issue between the Z80 I have in the ICE and the Z80 the Superbrain had fitted. The difference is, one is a genuine Zilog Z80 (Z84C002OPEC) whereas the other one is a MOSTEK Z80 (MK3880-M4).

It seems to be detecting more RAM (with OUT 6B,82 followed by OUT 6A,B2):

Code: Select all

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
000000000000000011111111111111112222222222222222
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF


I consider this a bit odd. And Bank 3 is still missing!

jonb
Posts: 1689
Joined: Sat May 21, 2011 12:42 pm
Location: South Coast of England

Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 8:44 pm

Musing on the keyboard decoder, I wonder if it really is gone, or just not being initialised properly, or is getting some sort of bad signal. The problem is that, reading the datasheet, it appears that the mapping of keys to values is encoded in ROM, which is programmed at the factory. If the data bus buffering is shot, so too is the chip, and a replacement will not be easy to acquire.

It's certainly the cause of the data bus problem, but is it due to chip failure? I sure hope not! For now, it is off the board, and restoring ROM access to CPU1 is the next priority.

Any comments on the CPU swap?


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