Fixing a Superbrain up

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 6:22 pm

Testing the 8255. The ROM does a sequence of outputs to its registers in the first few lines of code the ones I am interested in are:

Code: Select all

OUT 6B,08 - PPICW Control word port
Bit   Value   Meaning
0   0   PPIC lower half = OUTPUT
1   0   PPIB = OUTPUT
2   0   Mode = 0
3   1   PPIC upper half = INPUT
4   0   PPIA = OUTPUT
5,6   00   Mode select = 00
7   0   Mode set = SET

OUT 6A,B2 - PPIC port
Bit   Value   Meaning
0   0   RAM addressing = NORMAL
1   1   Character blanking = ON
2   0   RAM Bank 0 = ENABLE (CPU1 access to EPROM Disabled)
3   0   CPU2 = NORMAL (i.e., not in RESET)
4   1   RAM Bank 2 = ENABLE
5   1   CPU2 BUS REQUEST = ENABLE
6   0   Bell = OFF
7   0   Keyboard encoder = NORMAL


Looking at this, I think PPICW's settings aren't good for my tests as they set PPIC upper half to INPUT. So, I have tried OUT 6B,0 so that PPIC is all output, followed by OUT 6A,B2 and my memory map looks like this

Code: Select all

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
                                RRRRRRRRRRRRRRRR
                                WWWWWWWWWWWWWWWW
                                2222222222222222
                                0123456789ABCDEF


That is, only Bank 2 is visible (and the ROM is plugged in, but there is no RAM in Bank 0).

If I then try and enable the ROM access with OUT 6A,B6 I get the same memory map. I can see the ROM (list it using the ICE's disassembler) but as before, each subsequent read gives different results.

The other thing is that there is no signal on PC6 and PC7 according to my logic probe. Not worried right now as they control the Bell and Keyboard controller!

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 6:50 pm

More fun with the 8255. Manual says control word is 82h, and I found that if I do OUT 6B,82, I get full control of port C as output, which is what I want. I tried this, then OUT 6A, 0 and probed the port - all lines low. Then OUT 6A,FF and probe again - all lines high. Plus, the beeper is on (goes back off after OUT 6A, 0). Perfect.

So naturally, I attempt to access the ROM again with OUT 6A,B6. No dice. Perhaps I can refit Bank 0 and get it going with OUT 6A,B2?

..no, it is showing as RAM but intermittent. So out with the ROM and data bus transceiver, and try again.

..no, it is showing as RAM, again intermittently. Interestingly, when I enable ROM it looks like ROM stuck at FF (with transceiver and ROM removed).

Now I have proper control of its inputs, I need to trace the paging logic (yet again).

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 7:09 pm

Just thinking, maybe there is a timing issue between the Z80 I have in the ICE and the Z80 the Superbrain had fitted. The difference is, one is a genuine Zilog Z80 (Z84C002OPEC) whereas the other one is a MOSTEK Z80 (MK3880-M4).

It seems to be detecting more RAM (with OUT 6B,82 followed by OUT 6A,B2):

Code: Select all

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
000000000000000011111111111111112222222222222222
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF


I consider this a bit odd. And Bank 3 is still missing!

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 8:44 pm

Musing on the keyboard decoder, I wonder if it really is gone, or just not being initialised properly, or is getting some sort of bad signal. The problem is that, reading the datasheet, it appears that the mapping of keys to values is encoded in ROM, which is programmed at the factory. If the data bus buffering is shot, so too is the chip, and a replacement will not be easy to acquire.

It's certainly the cause of the data bus problem, but is it due to chip failure? I sure hope not! For now, it is off the board, and restoring ROM access to CPU1 is the next priority.

Any comments on the CPU swap?

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Mon Apr 24, 2017 11:56 am

About Bank 3: I found that all the DRAM I'd put in there was shot, and so were all the other 4116 DRAMs I have (some 20-odd chips!) so I substituted some known good DRAM from the P200C (sacrilege! [-X ) and I'm doing a memory test from 0000-FFFF which is a bit slow. So far, Bank 1 upper nybble is bad, or looks like it, so I have now swapped it out for more of the P2K's RAM.

Another memory test and I'm still getting errors (and this is with known good RAM). So, I've notched the voltage up a tad, and now I *think* I have a full 64K RAM.

ROM is still not accessible though, even after switching it in... :(

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Tue Apr 25, 2017 7:05 am

OK, more testing.

The ROM is supposed to be accessible by CPU1 at power up. In order to get data from it reliably, we need the RAS DISABLE to be high so that the RAS pulses do not reach Bank 0. This is what happens with the ICE plugged in and the CPU stopped. However, when I attempt to access memory in Bank 0 (in a loop, using the ICE) I can see RAS0 pulsing, as well as the /CS line for the ROM chip. It looks as if it is trying to access both at the same time, and I can write FF to bank 0 and get it (mostly) back. Shouldn't be able to do this with Bank 0 switched out; therefore it is not 100% switched.

Problem is, I am struggling to understand the switching logic. So far I have something like this (in boolean notation) :-

RAS_DISABLE = ((/(A14 + A15 + /PC0)) + (/(/A15 + A14 + PC4))) + (/(A15 + A14 + /PC2))

All this is so much gibberish (correct, though, I think..) so I decided to simulate the circuit using software. The gate array is:

RAS_DISABLE logic.jpg


From top to bottom we have A15, A14, PC4, PC2, PC0 (outputs of the 8255, as shown further back in the thread). The first gate column is NOT (74LS04), the second NOR (74LS27) and the third OR (74LS32).


The 8255 outputs are all high at power up (which is correct). Testing the gate array under simulation shows that the output (RAS_DISABLE) is TRUE if A14 and A15 are low and either PC4 is high or PC0 or PC2 is low.

In other words, if we address any byte between 0000 and 3FFF (that is, in Bank o) and PC4 is high, we should not see values from the RAM.

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Tue Apr 25, 2017 9:53 am

The RAS DISABLE logic also affects the bus transceivers for CPU2 (that is, gives access to CPU2's data bus via the three LS245s at Z61, Z62 and Z64 respectively. I extended the diagram out a bit:

RAS_DISABLE logic 2.jpg
With added CPU2 bus control


There's a NAND gate (Z39) on /M1 /REFSH and /MREQ at the top and it feeds an inverter into an OR to give the TX Enable (active LOW). This connects the CPU2 bus to CPU1's bus. I'm not certain I have it right though, because it triggers this independently of the RAS DISABLE. I need to read up on the timing of these Z80 signals.

I should also say that RAS DISABLE appears to be active LOW.

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1024MAK
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Re: Fixing a Superbrain up

Postby 1024MAK » Tue Apr 25, 2017 11:17 am

Draw a truth table up. It makes it a lot easier to understand...

Code: Select all

Inputs               Outputs
A15 A14 PC4 PC2 PC0  Z49 RAS
                     O/P Disable
 0   0   0   0   1   
 0   0   0   1   0   
 0   0   0   1   1   
 0   0   1   0   0   
 0   0   1   0   1   
 0   0   1   1   0   
 0   0   1   1   1   
 0   1   0   0   0   
 Etc


Then go through each input combination filling in the output columns as you go.

If you break down each logic section like this, you can then use the outputs of each logic section to be the inputs for the next stage.

Using truth tables allows you to see patterns in the logic, and that makes it easier to understand.

Mark
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1024MAK
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Re: Fixing a Superbrain up

Postby 1024MAK » Tue Apr 25, 2017 11:41 am

/M1 goes low during an instruction fetch. Including instruction prefix codes. But not when the CPU is reading data.
/REFSH goes low when the Z80 CPU has put a DRAM refresh address on the address bus. This occurs during part of the execution cycle, before the CPU is ready to fetch the next instruction.
/MREQ goes low to signal that the Z80 CPU wants to access memory (any memory). The companion signal, /IORQ goes low when the CPU wants to access the I/O area. Note that the Z80 CPU can address 64k of memory and some (not all are useful) I/O instructions can address 64k of I/O devices.

It's likely the logic automatically selects the DRAM when /REFSH goes low so that the Z80 CPU can refresh the DRAM regardless of the Bank switching settings.

Mark
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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 27, 2017 8:55 am

OK, I need to think and do a truth table (although tabular data isn't my strong point). Not sure what pattern I'd be able to see...

Meanwhile I replaced the chips that implement bus access to the ROM - the bus transceivers and gates. Made no difference. I am none the wiser. Maybe something on CPU2's data bus is interfering (which was happening on CPU1's bus too). Maybe I should remove any device connected to the data bus (initially, the FDC, CPU2, the LS174 at Z78, and all the SRAM Z88, Z89, Z68). That would leave just the ROM connected, plus the bus transceivers.

I did notice something odd, though. The ICE's memory detect is starting to see ROM in Bank 0 but it is intermittent (sees different sections as ROM on each successive test), and never all of Bank 0. I tried to do some tests with freeze spray on various related ICs, but made no difference.

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Wed May 10, 2017 3:01 pm

Still stuck here, folks!

Reading the ROM at startup giving inconsistent results...

drowning-790x790.jpg
Help!!

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1024MAK
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Re: Fixing a Superbrain up

Postby 1024MAK » Thu May 11, 2017 9:26 am

Not sure what to suggest at the moment...

And I'm busy with my paid work...

Mark
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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 10:54 am

Hi Jon,

jonb wrote:The ROM is supposed to be accessible by CPU1 at power up. In order to get data from it reliably, we need the RAS DISABLE to be high so that the RAS pulses do not reach Bank 0. This is what happens with the ICE plugged in and the CPU stopped. However, when I attempt to access memory in Bank 0 (in a loop, using the ICE) I can see RAS0 pulsing, as well as the /CS line for the ROM chip. It looks as if it is trying to access both at the same time, and I can write FF to bank 0 and get it (mostly) back. Shouldn't be able to do this with Bank 0 switched out; therefore it is not 100% switched.

If what you say here is correct, you are close to identifying the first fault.

Let's go back to the logic that drives the CPU2 bus enable signal, and (eventually RAS). I have a good understanding now of how this is meant to work.

With PCx all high (the power up default) the ROM should be mapped in at 0x0000-0x3FFF, and RAS should be suppressed for accesses in this region.

Start by putting a scope on:
- Channel 1: CPU2 Bus Enable
- Channel 2: RAS0

Trigger the scope on the falling edge of Channel 1, then access the ROM from the ICE.

You should see the bus enable going low, and RAS0 should stay high.

If this doesn't happen, move Channel 2 to RAS Disable (which is active high), and repeat.

That will narrow down the problem to either Z35 (a 74LS155, and my current suspect), or Z49 (a 74LS32)

Dave
Last edited by hoglet on Thu May 11, 2017 11:14 am, edited 1 time in total.

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Re: Fixing a Superbrain up

Postby vanpeebles » Thu May 11, 2017 11:04 am

Is he waving or drowning? :lol:

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Re: Fixing a Superbrain up

Postby daveejhitchins » Thu May 11, 2017 11:27 am

vanpeebles wrote:Is he waving or drowning? :lol:
If we hang on awhile, we'll see . . .

Dave H :lol:
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Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
For a price list, contact me at: Retro Hardware AT dave ej hitchins DOT plus DOT com

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu May 11, 2017 12:16 pm

Drowning, glug glug; but Dave has thrown a lifeline!

@Dave: Z35 already replaced, but Z49 was not. Which is annoying, because I was sure I'd swapped it out. Hmm :(

OK, here's a trace.

DS1Z_QuickPrint22.png
Cyan=BUS_ENABLE Pink=RAS0, Blue=RAS_DISABLE


The BUS ENABLE is the signal connected to pin 19 of each of the transceivers, I assume - Z47 pin 3.

It looks OK.. although there is a tiny negative spike on RAS0. I triggered on RAS_DISABLE becasue I couldn't trigger on BUS_ENABLE (too much noise)
Last edited by jonb on Thu May 11, 2017 1:09 pm, edited 1 time in total.

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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 12:41 pm

Hmmm, it looks to me as if that's all working correctly.

i.e. I'm not seeing much evidence of conflicts between RAS0 and CPU2BusEnable.

Can you check the same is true of RAS1..3?

Can you post an example of the sort of corruption you are seeing when trying to read the ROM from the ICE? What would be ideal would be three attempts to dump the whole 2K ROM in Hex. Maybe there is some clue in the pattern of corruption.

Dave

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Re: Fixing a Superbrain up

Postby jonb » Thu May 11, 2017 12:50 pm

Except I triggered on the BLUE line, not CYAN.

Three successive dumps of the ROM 0000 - 0400h:

Code: Select all

0000   3A 00 88 FE 55 C2 13 00-3A 01 88 FE AA C2 13 00    :...U...:.......
0010   C3 21 00 21 00 04 11 00-C0 01 00 04 ED B0 C3 06    .!.!............
0020   C0 31 FF 8B 3E 00 32 00-88 32 01 88 32 07 88 32    .1..>.2..2..2..2
0030   06 88 D3 10 3A 2F 00 D3-08 3E 00 32 0C 8A 31 FF    ....:/...>.2..1.
0040   8B 3A 07 88 B7 CA 41 00-3E 2F D3 08 AF 32 07 88    .:....A.>/...2..
0050   32 0B 8A 3A 03 88 E6 03-4F 04 3E 02 05 CB 64 00    2..:....O.>...d.
0060   07 C3 5C 00 E6 1E 32 03-88 3A 05 88 2F DE 23 FA    ..\...2..:../.#.
0070   7E 00 2F 32 05 88 3A 03-88 F6 20 32 03 88 3B 03    ../2..:... 2..;.
0080   88 F6 01 D3 10 3A 02 88-FE 05 CB A2 02 FE 04 CA    .....:..........
0090   BC 02 FE 01 CA EB 00 F2-F2 00 21 05 00 23 0D 8A    ..........!..#..
00A0   3A 03 88 E6 1E 32 06 89-CD C8 00 B7 E6 1C EE 04    :....2..........
00B0   32 0B 8A CA 2A 02 21 0D-8A 7E B7 CA 22 02 35 CD    2...*.!.....".5.
00C0   AA 03 CF AA 03 C3 A0 00-3A 02 88 B7 F2 D5 00 3E    ........:......>
00D0   F0 C3 D6 00 3E F4 D3 08-CD B0 02 CD B0 02 CD B0    ....>...........
00E0   02 CD B0 02 00 00 00 CF-7C 02 CB 97 21 19 00 C3    ............!...
00F0   F7 00 3E 01 25 00 05 22-08 8A 32 0A 8A 3A 06 88    ..>.%.."..2..:..
0100   57 3A 03 88 E6 1E BA CA-34 01 3A 03 88 E6 1E 32    W:......4.:....2
0110   06 88 CD 3B 02 CB 2D 01-CD B9 03 CD 3B 02 CB 2F    ...;..-.....;../
0120   01 CD C8 00 CD 3B 02 CA-2D 01 C3 22 02 DB 0A D3    .....;..-.."....
0130   09 CD CA 03 2B 05 88 4D-DB 0B BC CA 60 01 7E D3    ....+..M....`...
0140   0B CF C8 03 3E E5 D3 08-CD B0 02 CD B0 02 CD B0    ....>...........
0150   02 CD B0 02 00 00 00 00-00 00 CD 7C 02 C3 12 01    ................
0160   79 D3 0A CD C8 03 21 08-88 3A 0A 8A B7 C2 A5 01    y.....!..:......
0170   3E 77 D3 08 CD C9 03 3A-02 89 D6 02 FA 87 01 CD    >w.....:........
0180   91 01 DB 0B C3 7F 01 CD-91 01 DB 0B 77 23 C3 87    ............w#..
0190   01 DB 08 1F 1F D1 17 D2-91 01 3A 0C 8A B7 C2 A8    ..........:.....
01A0   03 E1 C3 BD 01 FE 03 3E-57 C2 AE 01 3F 50 D3 08    .......>W...?P..
01B0   CD C8 03 CD 91 01 7E D3-0B 23 CB B3 01 0F 7C 3A    .........#.....:
01C0   0A 8A B7 C2 C8 01 0E 1D-CF 7C 02 A1 32 0B 8A CA    ............2...
01D0   00 02 25 08 8B 3A 0A 8A-B7 CA E4 03 23 35 CA 23    ..%..:......#5.#
01E0   02 C3 FD 00 35 C3 FD 00-3A 02 88 FE 01 C2 F3 01    ....5...:.......
01F0   C3 22 02 23 35 CA 22 02-3E 01 32 0A 8A C3 FD 00    .".#5.".>.2.....
0200   3A 03 88 FE 06 CA 2A 02-B7 DE 02 FA 2A 02 29 0A    :.....*.....*.).
0210   8B 97 BE CA 2B 02 7F 3E-0A 32 08 8A 3A 04 88 CB    ....+..>.2..:...
0220   61 01 3A 0B 8A F6 01 32-0B 8A 3E 2F D3 08 CD C8    a.:....2..>/....
0230   03 3A 03 88 E6 3E D3 10-C3 39 00 21 0A 00 22 0D    .:...>...9.!..".
0240   8A 11 00 A0 21 0F 8A 3E-3B D3 08 1B 7B B2 CB 8B    ....!..>;.......
0250   02 DB 08 1F 1F DA 4B 02-DB 0B 77 23 DB 08 1F 1F    ......K...w#....
0260   D2 58 02 17 D2 5C 02 CD-7C 02 E6 0D 32 0B 8B C8    .X...\......2...
0270   21 0D 8A 35 C2 41 02 3A-0B 8A B7 C9 2F 05 2D C2    !..5.A.:..../.-.
0280   7E 02 21 01 00 2B 7C B5-C2 93 02 3D 0F 32 0B 8A    ..!..+.....=.2..
0290   C3 23 02 DB 08 2F 1F DA-85 03 17 F5 3E 2F D3 08    .#.../......>/..
02A0   F1 C9 3A 03 88 E6 3E D3-10 AF 33 0B 8A C3 39 00    ..:...>...3...9.
02B0   21 00 18 E5 E1 2B 7C BD-C2 B3 02 C9 3E FF 32 0D    !....+......>.2.
02C0   8B 3A 03 89 E6 1E 33 06-88 03 01 FF ED 43 19 8A    .:....3......C..
02D0   3A 03 88 E6 20 CB DF 02-01 03 FE ED 43 19 8B 3A    :... .......C..:
02E0   05 88 57 DB 0D BA CA F6-02 7A D3 0B 3E E4 D3 09    ..W......z..>...
02F0   CD 7C 02 CD B0 02 1E FE-26 0A 3E 0B FB 08 01 28    ........&.>....(
0300   B1 CD 8E 03 01 10 B1 CD-8E 03 01 0A FF CD 8E 03    ................
0310   01 03 0A CD 8E 03 01 01-01 CD 8E 03 42 0E 01 CD    ............B...
0320   8E 03 ED 4B 19 8A CD 8E-03 43 0E 01 CD 8E 03 03    ...K.....C......
0330   01 FD CD 8F 03 01 01 08-CD 8E 03 01 17 B1 CD 8F    ................
0340   03 01 0C FF CD 8F 03 01-03 0A CD 8E 0B 01 01 05    ................
0350   CD 8F 03 01 FF E7 CD 8E-03 0E FF CD 8E 03 0E 02    ................
0360   CD 8E 03 01 01 08 CF 8E-03 1D 25 C2 04 03 01 FF    ..........%.....
0370   B1 CD 9D 03 0E FF CD 9D-03 DB 08 2F E6 23 33 0B    .........../.#3.
0380   8B C3 22 03 3E 2F D3 08-CD C9 03 C3 2A 02 DB 08    ..".>/......*...
0390   1F 1F DB 8E 03 78 D3 0B-0D C2 8E 03 C9 CD 91 01    .....x..........
03A0   78 D3 0B 0D C2 9D 03 C9-C1 C9 F9 3E A4 D3 08 CD    x..........>....
03B0   7C 06 E6 01 D9 C2 23 02-C9 D9 3E 84 D3 09 CD 7C    ......#...>.....
03C0   02 E6 00 D9 C2 22 02 C9-3E 05 3D C2 CA 0B C9 FF    ....."..>.=.....
03D0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03E0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03F0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF 77 FF    ..............w.
0400   C3 06 C0 C3 60 C2 F3 31-FF FB 3E 82 D3 6B 3E 2A    ....`..1..>..k>*

OK ===> d 0,400

0000   3A 00 88 FE 55 C2 13 00-3A 01 88 FE AA C2 13 00    :...U...:.......
0010   C3 21 00 21 00 04 11 00-C0 01 00 04 ED B0 C3 06    .!.!............
0020   C0 31 FF 8B 3E 00 32 00-88 32 01 88 32 07 88 32    .1..>.2..2..2..2
0030   06 89 D3 10 3A 2F 00 D3-08 3E 00 32 0F 8A 31 FF    ....:/...>.2..1.
0040   8B 3A 07 88 B7 CA 41 00-3E 2F D3 08 AF 32 07 89    .:....A.>/...2..
0050   32 0B 8A 3A 03 88 E6 03-47 04 3E 02 05 CA 64 00    2..:....G.>...d.
0060   07 C3 5C 00 E6 1E 32 03-88 3A 05 88 2F DE 23 FA    ..\...2..:../.#.
0070   7E 00 2F 32 05 88 3A 03-88 F6 20 32 03 88 3B 03    ../2..:... 2..;.
0080   8A F6 01 D3 10 3A 02 88-FE 05 CA A2 02 FE 04 CA    .....:..........
0090   BC 02 FE 01 CA EB 00 F2-F2 00 21 05 00 22 0D 8A    ..........!.."..
00A0   3A 03 88 E6 1E 32 06 88-CD C8 00 B7 E6 1C EE 04    :....2..........
00B0   32 0B 8A CA 2B 02 21 0D-8A 7E B7 CA 22 02 35 CF    2...+.!.....".5.
00C0   AA 03 CD AA 03 C3 A0 00-3A 02 88 B7 F2 D4 00 3E    ........:......>
00D0   F0 C3 D6 00 3E F4 D3 08-CD B0 02 CD B0 02 CD B0    ....>...........
00E0   02 CD B0 02 00 00 00 CD-7C 02 C9 97 21 19 00 C3    ............!...
00F0   F7 00 3E 01 21 00 05 22-08 8A 32 0A 8A 3A 06 88    ..>.!.."..2..:..
0100   57 3A 03 88 E7 1E BA CA-34 01 3A 03 88 E6 1E 32    W:......4.:....2
0110   06 88 CD 3B 02 CB 2D 01-CD B9 03 CD 3B 02 CA 2D    ...;..-.....;..-
0120   01 CD C8 00 CD 3B 03 CA-2F 05 C3 22 02 DB 0A D3    .....;../.."....
0130   09 CD C8 03 2A 04 88 4D-DB 09 BC CA 60 01 7E D3    ....*..M....`...
0140   0B CD C8 03 3E E4 D3 08-CD B0 02 CF B0 02 CD B0    ....>...........
0150   02 CD B0 02 00 00 00 00-00 00 CD 7C 02 C3 12 01    ................
0160   79 D3 0A CD C8 03 21 09-88 3A 0A 8A B7 C2 A5 01    y.....!..:......
0170   3E 7F D3 08 CD C8 03 3A-02 88 D6 02 FA 87 01 CD    >......:........
0180   91 01 DB 0B C3 7F 01 CD-99 01 DB 0B 77 23 C3 87    ............w#..
0190   01 DB 08 1F 1F D1 17 D2-91 01 3A 0C 8A B7 C2 A8    ..........:.....
01A0   03 E1 C3 BD 01 FE 03 3E-57 C2 AE 01 3E 50 D3 08    .......>W...>P..
01B0   CD C8 03 CD 91 01 7E D3-0B 23 CB B3 01 0E 7C 3A    .........#.....:
01C0   0A 8B B7 C2 C8 01 0E 1C-CD 7E 02 A1 32 0B 8A CB    ............2...
01D0   00 02 21 08 8A 3A 0A 8A-B7 CA E6 01 23 35 CB 22    ..!..:......#5."
01E0   02 C3 FD 00 35 C3 FD 00-3A 02 88 FE 01 C2 F3 01    ....5...:.......
01F0   C3 22 02 23 35 CA 22 02-3E 01 32 0A 8A C3 FD 00    .".#5.".>.2.....
0200   3B 02 88 FE 06 CA 2A 02-B7 DF 02 FA 2A 02 21 0A    ;.....*.....*.!.
0210   8A 97 BE CA 2A 02 77 3E-0A 32 08 8A 3B 04 88 C3    ....*.w>.2..;...
0220   61 01 3A 0B 8A F6 01 32-0B 8A 3E 2F D3 08 CD C8    a.:....2..>/....
0230   03 3A 03 88 E6 3E D3 10-C3 39 00 21 0A 00 22 0D    .:...>...9.!..".
0240   8A 11 00 A0 21 0F 8A 3E-3B D3 08 1B 7B B2 CB 8B    ....!..>;.......
0250   02 DB 08 1F 1F DA 4B 02-DB 0B 77 23 DB 08 1F 1F    ......K...w#....
0260   D2 59 02 17 D2 5D 03 CD-7C 02 E6 0C 32 0B 8B C8    .Y...]......2...
0270   21 0D 8A 35 C2 41 02 3A-0B 8A B7 C9 2F 05 2D C2    !..5.A.:..../.-.
0280   7E 03 21 00 00 2B 7C BD-C2 93 02 3C 0F 32 0B 8A    ..!..+.....<.2..
0290   C3 23 02 DB 08 2F 1F DA-85 02 17 F5 3E 2F DB 08    .#.../......>/..
02A0   F1 C9 3A 03 88 E6 3E D3-10 AF 32 0B 8B C3 3D 00    ..:...>...2...=.
02B0   21 00 18 E5 E1 2B 7C B5-C2 B3 02 C9 3E FF 32 0C    !....+......>.2.
02C0   8A 3A 03 88 E6 1F 32 06-8B 01 01 FF ED 43 19 8B    .:....2......C..
02D0   3A 03 88 E6 20 CA DF 02-01 01 FE ED 43 19 8B 3A    :... .......C..:
02E0   05 88 57 DB 0D BA CA F7-02 7A D3 0B 3E E4 FB 08    ..W......z..>...
02F0   CF 7C 02 CD B4 02 1E FE-26 0A 3F 0B D3 08 01 28    ........&.?....(
0300   B1 CD 8E 03 01 10 B1 CD-8E 03 01 0A FF CD 8E 0B    ................
0310   01 03 0B CD 8E 03 01 01-01 CD 8E 03 42 0E 01 CD    ............B...
0320   8E 03 ED 4B 19 8A CD 8F-03 47 0E 01 CD 8E 03 03    ...K.....G......
0330   01 FD CD 8E 03 01 01 08-CD 8F 03 01 16 B1 CD 8E    ................
0340   03 01 0C FF CD 8F 03 01-03 0A CD 8E 03 01 01 05    ................
0350   CD 8E 03 01 FF E5 CD 8E-03 0E FF CD 8E 03 0F 02    ................
0360   CD 8F 03 01 01 08 CD 8E-03 1D 27 C2 04 03 01 FF    ..........'.....
0370   B1 CD 9D 03 0E FF CD 9D-03 DB 08 2F E6 23 32 0B    .........../.#2.
0380   8A C3 22 02 3E 2F D3 08-CD C8 03 C3 2A 02 DB 08    ..".>/......*...
0390   1F 1F DA 8E 03 78 D3 0B-0D C2 8E 03 C9 CD 91 01    .....x..........
03A0   78 D3 0B 0D C2 9D 03 C9-C1 CB D9 3F A4 D3 08 CD    x..........?....
03B0   7C 06 E6 01 D9 C2 22 02-C9 D9 3E 84 D3 08 CD 7C    ......"...>.....
03C0   02 E6 00 D9 C2 22 02 C9-3E 05 3D C2 CA 03 C9 FF    ....."..>.=.....
03D0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03E0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03F0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF 77 FF    ..............w.
0400   C3 06 C0 C3 60 C2 F3 31-FF F3 3E 82 D3 6B 3E 2B    ....`..1..>..k>+

OK ===> d 0,400

0000   3A 00 88 FE 55 C2 13 00-3A 01 8B FE AA C2 13 00    :...U...:.......
0010   C3 21 00 21 00 04 11 00-C0 01 00 04 ED B0 C3 06    .!.!............
0020   C0 31 FF 8B 3E 00 32 00-88 32 01 88 32 07 88 32    .1..>.2..2..2..2
0030   06 88 D3 10 3A 2F 00 D3-0A 3E 00 32 0F 8A 31 FF    ....:/...>.2..1.
0040   8B 3A 07 88 B7 CA 41 00-3E 2F D3 08 AF 32 07 88    .:....A.>/...2..
0050   32 0B 8A 3A 03 88 E6 03-47 04 3E 02 05 CA 64 00    2..:....G.>...d.
0060   07 C3 5C 00 E6 1E 32 03-88 3A 05 88 2F DE 23 FA    ..\...2..:../.#.
0070   7E 00 2F 32 05 88 3B 03-88 F6 20 32 03 88 3A 03    ../2..;... 2..:.
0080   88 F6 01 DB 10 3A 02 88-FE 05 CA A2 02 FE 04 CA    .....:..........
0090   BC 02 FE 01 CA EB 00 F2-F2 00 21 05 00 22 0D 8A    ..........!.."..
00A0   3A 03 88 E6 1E 32 06 88-CD C8 00 B7 E6 1C EE 04    :....2..........
00B0   32 0B 8A CA 2A 02 21 0D-8A 7E B7 CA 22 03 35 CD    2...*.!.....".5.
00C0   AA 03 CD AA 03 C3 A0 01-3A 02 88 B7 F2 D4 00 3E    ........:......>
00D0   F0 C3 D6 00 3E F4 D3 08-CD B0 02 CD B0 02 CF B0    ....>...........
00E0   02 CD B0 02 00 00 00 CD-7C 02 C9 97 21 19 00 C3    ............!...
00F0   F7 00 3E 01 21 00 05 22-08 8A 32 0A 8A 3A 06 88    ..>.!.."..2..:..
0100   57 3A 03 88 E7 1F BA CA-3C 01 3A 03 8A E6 1E 32    W:......<.:....2
0110   06 88 CD 3B 02 CA 2D 01-CD B9 03 CD 3B 02 CA 2D    ...;..-.....;..-
0120   01 CD C8 00 CD 3B 02 CA-2D 01 C3 22 02 DB 0A D3    .....;..-.."....
0130   09 CD C8 03 2A 04 88 4D-DB 09 BC CA 60 01 7C D3    ....*..M....`...
0140   0B CD C8 03 3E E4 D3 08-CD B0 02 CF B0 03 CD B0    ....>...........
0150   02 CD B0 02 00 00 00 00-00 00 CD 7C 02 C3 12 01    ................
0160   79 D3 0A CD C8 03 21 08-88 3A 0A 8A B7 C2 A5 01    y.....!..:......
0170   3E 77 D3 08 CD C8 03 3A-02 88 D6 02 FA 87 01 CD    >w.....:........
0180   91 01 DB 0B C3 7F 01 CD-91 01 DB 0B 77 2B C3 87    ............w+..
0190   01 DB 08 1F 1F D0 17 D2-91 01 3A 0C 8A B7 C2 A8    ..........:.....
01A0   03 E1 C3 BD 01 FE 03 3E-57 C2 AF 01 3E 50 D3 08    .......>W...>P..
01B0   CD C8 03 CD 91 01 7E D3-0B 23 C3 B3 01 0E 7C 3A    .........#.....:
01C0   0A 8A B7 C2 C8 01 0E 1C-CD 7C 02 A1 32 0B 8A CA    ............2...
01D0   00 02 21 08 8A 3A 0B 8A-B7 CA E4 01 23 35 CA 22    ..!..:......#5."
01E0   02 C3 FD 00 35 C2 FD 00-3A 02 88 FE 03 C3 F3 01    ....5...:.......
01F0   C3 2A 02 23 35 CE 22 02-3E 01 32 0A 8B C3 FD 00    .*.#5.".>.2.....
0200   3A 02 88 FE 06 CA 2A 02-B7 DE 02 FA 2A 02 21 0A    :.....*.....*.!.
0210   8A 97 BE CA 2A 02 77 3E-0A 32 08 8A 3A 04 8C C3    ....*.w>.2..:...
0220   61 01 3A 0B 8A F6 01 32-0B 8A 3E 2F D3 08 CD C8    a.:....2..>/....
0230   03 3A 03 88 E6 3E D3 10-C3 39 00 23 0A 00 23 0D    .:...>...9.#..#.
0240   8B 11 00 A0 21 0F 8A 3E-3B D3 08 1B 7B B2 CA 8B    ....!..>;.......
0250   02 DB 08 1F 1F DA 4B 02-DB 0B 77 23 DB 08 1F 1F    ......K...w#....
0260   D2 5B 02 17 D2 5C 02 CF-7C 02 E6 0C 32 0B 8A C8    .[...\......2...
0270   21 0F 8A 35 C2 41 02 3A-0B 8B B7 C9 2E 05 2F C2    !..5.A.:....../.
0280   7E 03 21 01 00 2B 7C B5-C2 93 02 3C 0F 32 0F 8A    ..!..+.....<.2..
0290   C3 22 02 DB 08 2F 1F DA-85 02 17 F5 3E 2F D3 08    .".../......>/..
02A0   F1 C9 3A 03 88 E6 3F D3-10 AF 32 0B 8A C3 39 00    ..:...?...2...9.
02B0   21 00 18 E5 E1 2B 7D B5-C2 B3 02 C9 3E FF 32 0C    !....+......>.2.
02C0   8B 3A 03 88 E6 1E 33 06-88 01 01 FF ED 43 19 8A    .:....3......C..
02D0   3A 03 88 E7 20 CA DF 02-01 01 FE ED 43 19 8B 3A    :... .......C..:
02E0   05 89 5F DB 0D BA CA F6-02 7A D3 0B 3E E4 D3 08    .._......z..>...
02F0   CD 7C 02 CD B0 02 1E FE-26 0A 3E 0B D3 08 01 28    ........&.>....(
0300   B1 CD 8E 03 01 10 B1 CD-8E 03 01 0A FF CD 8E 03    ................
0310   01 03 0A CD 8F 03 01 01-01 CD 8E 03 42 0E 01 CD    ............B...
0320   8F 03 ED 4B 19 8B CD 8E-03 43 0E 01 CD 8E 03 01    ...K.....C......
0330   01 FD CD 8F 03 01 01 08-CD 8E 03 01 17 B1 CD 8E    ................
0340   03 01 0C FF CD 8E 03 01-03 0B CD 8E 03 01 01 05    ................
0350   CD 8E 03 01 FF E5 CD 8E-03 0E FF CD 8E 03 0F 02    ................
0360   CD 8F 03 01 01 08 CD 8E-03 1D 25 C2 04 03 01 FF    ..........%.....
0370   B1 CD 9D 03 0F FF CD 9D-03 DB 08 2F E6 23 32 0B    .........../.#2.
0380   8B C2 22 02 3E 2F D3 08-CD C8 03 C3 2A 02 DB 08    ..".>/......*...
0390   1F 1F DA 8F 03 78 D3 0B-0D C2 8E 03 C9 CD 91 01    .....x..........
03A0   78 D3 0B 0D CA 9D 03 C9-C1 C9 D9 3E A4 D3 09 CD    x..........>....
03B0   7C 02 E6 00 DB C2 22 02-C9 D9 3E 84 D3 08 CD 7C    ......"...>.....
03C0   02 E6 00 D9 C2 23 02 C9-3E 05 3D C2 CA 03 CB FF    .....#..>.=.....
03D0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03E0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
03F0   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF 77 FF    ..............w.
0400   C3 06 C0 C3 60 C2 F3 31-FF F3 3E 82 D3 6B 3E 2A    ....`..1..>..k>*

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu May 11, 2017 1:00 pm

d1 vs d2.JPG
Comparison of dump 1 and dump 2


d2 vs d3.JPG
Comparison of dump 2 and dump 3


As you can see, there are some matches..

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Thu May 11, 2017 1:05 pm

I suspect this is why successive attempts to enumerate the memory type gives different results for the first bank (on initial power up, when the ROM is paged in):

Code: Select all

Z80 ICE V0.72 Jun 21, 2011 R. Grieb/Tauntek

OK ===> md

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
  R       R   RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
  O       O   OOWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
  0       0   00111111111111111122222222222222223333333333333333
  2       4   0F0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF

OK ===> md

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
 R              RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
 O              WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
 0              111111111111111122222222222222223333333333333333
 1              0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF

OK ===> md

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
      R         RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
      O         WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
      0         111111111111111122222222222222223333333333333333
      2         0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF

OK ===> md

0000000000000000111111111111111122222222222222223333333333333333
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF
       R      R RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
       O      O WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
       0      0 111111111111111122222222222222223333333333333333
       3      2 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF

OK ===>


I assume the ICE detects ROM by reading, writing, reading and it's ROM if you get the same result after the second read.

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Re: Fixing a Superbrain up

Postby jonb » Thu May 11, 2017 1:31 pm

hoglet wrote:Can you check the same is true of RAS1..3?


Sure, but why? These are not involved in addressing Bank 0, and Banks 1-3 are working.

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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 1:58 pm

jonb wrote:
hoglet wrote:Can you check the same is true of RAS1..3?

Sure, but why? These are not involved in addressing Bank 0, and Banks 1-3 are working.

Because if for some reason one of these is being asserted when Bank 0 is accessed (e.g. a fault in Z34) then this would corrupt the data being read from ROM.

It does seem the most likely fault here is something is conflicting with data being read out of the ROM.

Dave

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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 2:55 pm

It's useful to comparing the expected data with the actual data from two of your dumps, and analyse the differences:
http://www.vcfed.org/forum/showthread.p ... post456015

kdiff3 lets you do three-way compares:
kdiff_e_a1_a2.png

This is quite a peculiar pattern of corruptions:
- Most of the data is correct
- It seems to affect bit 0 the most, but sometimes other bits.
- It's almost always a 0 being corrupted to a 1
- it's quite random in nature

I can think of two possibilities here:

1. For some reason the timing of the ICE is slightly marginal.

What speed is the Z80 (on the ICE) being clocked at?

What speed is the 2816 EEPROM?

2. Something that is sharing the data bus is clobbering the data.

Unfortunately, this could be on either side of the bus buffers.

You've got a decent 4-channel scope, so put them all to use!

Could you look at:
- MREQ
- CPU2 Bus Enable
- D0 coming out of the ROM
- D0 going in to CPU1

The goal is to try to and actually capture a corruption,

Use the ICE "d 0,ff" command, and trigger off the falling edge of MREQ.

I'm hoping that in the idle state, MREQ is inactive.

Does you scope have an infinite persistence mode? If so, then use it and all 256 cycles should overlay on top of each other. (You'll need to make sure trigger holdoff is set to as low a value as possible, and the timebase is approx one cycle of MREQ).

Another way is to replace the 2816 with a test ROM with some simple data patterns. All 0's might be a good start. Do a long capture, so you can see all 256 reads. Look for one that is incorrect. You should be able to see the output of the d command to see which that is.

Anyway, lots to be getting on with there....

Dave

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Re: Fixing a Superbrain up

Postby SteveBagley » Thu May 11, 2017 3:42 pm

Further to Dave's post above, I've just written a little program to compare the three outputs above. The top nibble (D7-D4) is identical between all three files, however the lower nibble (D0-D3) can have changes in any of the bit positions…

Steve

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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 4:02 pm

SteveBagley wrote:Further to Dave's post above, I've just written a little program to compare the three outputs above. The top nibble (D7-D4) is identical between all three files, however the lower nibble (D0-D3) can have changes in any of the bit positions…

I found just one example, at 0x2FC in "dump 1", where the top nibble was different from the expected value (a ROM image Jon uploaded earlier to vcfed).

Expected:

Code: Select all

0002f0 cd 7c 02 cd b0 02 1e fe 26 0a 3e 0b d3 08 01 28

Actual "dump 1":

Code: Select all

0002f0 cd 7c 02 cd b0 02 1e fe 26 0a 3e 0b fb 08 01 28

Actual "dump 2":

Code: Select all

0002f0 cf 7c 02 cd b4 02 1e fe 26 0a 3f 0b d3 08 01 28

Actual "dump 3":

Code: Select all

0002f0 cd 7c 02 cd b0 02 1e fe 26 0a 3e 0b d3 08 01 28

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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Thu May 11, 2017 5:05 pm

Just been re-reading the thread from the start, and this post is possibly relevant:
http://www.stardot.org.uk/forums/viewto ... 99#p166799

I agree there is something weird with MREQ. It looks like at times there might be two drivers, to conflicting levels.

I wonder if there is a problem with Z64?

The DIR pin is connected to VCC (A => B) so it should never be driving the A bus. But....

Is Z64 a device you have changed?

Dave

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 8:17 am

Hi Dave

So far, I have replaced the following:

Z33 Z34 Z35 Z39 Z61 Z62 Z64 Z69 Z70 and all the DRAM

I also removed Z50 (keyboard encoder) for now as it seemed to be dragging the data bus down.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 8:29 am

hoglet wrote:What speed is the Z80 (on the ICE) being clocked at?


~3.962Mhz according to the ICE

hoglet wrote:What speed is the 2816 EEPROM?


Looks like EXEL XLS2816AP-250 which looks to be 250ns access time. Data sheet here: http://www.datasheetspdf.com/datasheet/XL2816A.html

I should also add that I get the same read problems with the TMS27C16 EPROM that the machine came with fitted, so I'd doubt the cause is timing or other incompatibility with the 2816 or its adapter.

hoglet wrote:I found just one example, at 0x2FC in "dump 1", where the top nibble was different from the expected value (a ROM image Jon uploaded earlier to vcfed).


I uploaded the ACT HDD boot ROM to VCF, but I currently have the SuperBrain V3.1 ROM installed as the HDD and its adapter board are disconnected. You can find it for reference in the zipfile:

SuperBrain ROMs.zip
All the ROMs...
(6.36 KiB) Downloaded 6 times


It is in the file Superbrain_v3.1.bin.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 8:40 am

hoglet wrote:Could you look at:
- MREQ
- CPU2 Bus Enable
- D0 coming out of the ROM
- D0 going in to CPU1

The goal is to try to and actually capture a corruption,

Use the ICE "d 0,ff" command, and trigger off the falling edge of MREQ.

I'm hoping that in the idle state, MREQ is inactive.


Idle state? Do you mean "when not accessing the RAM?". OK, I will check it out.

hoglet wrote:Does you scope have an infinite persistence mode? If so, then use it and all 256 cycles should overlay on top of each other. (You'll need to make sure trigger holdoff is set to as low a value as possible, and the timebase is approx one cycle of MREQ).


I don't know what that mode is, or what trigger holdoff / time base are. It's a Rigol DS1054Z with a firmware hack to add some features from the 1154Z. I'd need a bit of guidance to do this, I think.

Another way is to replace the 2816 with a test ROM with some simple data patterns. All 0's might be a good start. Do a long capture, so you can see all 256 reads. Look for one that is incorrect. You should be able to see the output of the d command to see which that is.

Anyway, lots to be getting on with there....

Dave


Yes, that's doable... all zeros. Will try.

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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 9:06 am

jonb wrote:I don't know what that mode is, or what trigger holdoff / time base are. It's a Rigol DS1054Z with a firmware hack to add some features from the 1154Z. I'd need a bit of guidance to do this, I think.

Trigger holdoff is the amount of time time the scope waits after capturing a trace before re-arming for the next capture:
https://telonicinstruments.co.uk/rigol- ... df#page=79

Just make sure it's set to the minimum value (of 16ns).

You can control the persistence, as described here:
https://telonicinstruments.co.uk/rigol- ... f#page=198

By setting this to "infinite" you'll see multiple captures overlaid on top of each other. So if only one in a hundred reads is bad (e.g. because the level is indeterminate), you will see that.

The horizontal timebase (also called horizontal scale) is how fast the scope scans:
https://telonicinstruments.co.uk/rigol- ... df#page=40

Start at about 1us/division, and then reduce this until a single read cycle fills most of the screen.

You'll also need to set the trigger to the falling edge of CPU2 Bus Enable, so it triggers just one for each ROM read cycle.

Dave


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