Apple II problem.....

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Prime
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Apple II problem.....

Postby Prime » Mon Nov 13, 2017 9:39 am

Hi all,

I'm trying to cross port the DragonMMC hardware to work in an Apple II machine, seems simple right? So to this end and to allow me to prototype with one of my DragonMMC boards which I know the hardware is good on (as it's now in production). I built an Apple II slot to Dragon Cart port converter, ported the essential bits of the ROM from 6809 to 6502, and we should be good to go right?

This is where the problems start, my ROM code is working fine however at random when the 6502 is sending bytes to the AVR (via a CPLD), though the 6502 only sends one byte the AVR gets two (of the same value). I have a pin on the AVR that recieves an interrrupt when the 6502 writes to it's latch (buries within the CPLD). The value that comes over is correct, just repeated.

The interrupt signal is generated from the address bus (lower 4 bits), R/W, and an io decode provided on the Apple's slot that decodes a block of 16 addresses (16 for each slot), that is also aligned to phi0.

Just of notem the CPLD is an XC95144XL (3.3V but 5.0V tolerant), the apple bus of course is 5V.

my gut feeling is that perhaps I'm seeing a signal reflection issue here.

Comments anyone

Cheers.

Phill.

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sirmorris
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Re: Apple II problem.....

Postby sirmorris » Mon Nov 13, 2017 10:36 am

Remind me - are AVR interrupts edge or level triggered?

Prime
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Re: Apple II problem.....

Postby Prime » Mon Nov 13, 2017 1:15 pm

sirmorris wrote:Remind me - are AVR interrupts edge or level triggered?

Edge in this case falling edge, but you can also trigger on falling edge or low level.

I'm actually just latching the in and checking for it's flag in the main program loop.

Cheers.

Phill.

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sirmorris
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Re: Apple II problem.....

Postby sirmorris » Mon Nov 13, 2017 1:20 pm

Is the flag held high too long? Is it being recognised a second time? I think some logic analysing might be called for! To the logic analyser!

Prime
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Re: Apple II problem.....

Postby Prime » Mon Nov 13, 2017 7:25 pm

I *THINK* I have found the problem.

The Apple II has a block of IO addresses allocated to each slot 1..7 at $C080 + ($10 * Slot no), so I was doing my I/O by determining the slot number and then doing one of the floowing :

Code: Select all

   lda   reg_offs,x
   sta   reg_offs,x


Turns out when you do indexed addressing that the 6502 does a dummy read of the address followed by the real read (or write), this was of course causing the CPLD to ping the AVR, looks like it was just on the edge of the AVR's response time, so with a slower AVR clock, the first read would effectively be ignored.

Changing the code to use absolute addresses has cured the double reads, though the interface isn't working correctly yet, it's getting further than it was :)

Cheers.

Phill.

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hoglet
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Re: Apple II problem.....

Postby hoglet » Mon Nov 13, 2017 8:31 pm

Doh! That's caught be out a couple of times as well.

It should be only the STA that is doing the dummy read (unless you are crossing a page boundary, which I don't think you are).

Dave

Prime
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Re: Apple II problem.....

Postby Prime » Tue Nov 14, 2017 12:22 am

hoglet wrote:Doh! That's caught be out a couple of times as well.

It should be only the STA that is doing the dummy read (unless you are crossing a page boundary, which I don't think you are).


Nope not crossing a page boundry, was really frustrating me as the CPLD and AVR code are well tested and deployed on the DragonMMC board and working without these issues...and the 65xx bus is effectivly the same as the 68xx bus :( One of those things that catches you when you are not looking. Not caught me before as when I worked on the AtoMMC code that's all doing I/O to absolute locations so no dummys :)

Cheers.

Phill.


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