Certainly if the ACIA Tx Interrupt is slow to be serviced, then the ACIA master reset write would be delayed.Diminished wrote: ↑Tue Jun 21, 2022 5:06 pmCould it have something to do with the hardware configuration of the machine that wrote out each individual tape? More frequent IRQs on those machines or something?
i.e. there clearly the potential for a race condition between the interrupt handler and the first of the two extra bytes.
This might allow part of the first byte of extra data to "leak out".
Can you say anything about the range of values you see when this extra byte is present. Are the higher numbered bits typically '1'?
The interrupt might be slow to be serviced if another interrupt is pending. But think is unlikely to affect all blocks in the same program equally. It would be pretty random.
I wonder if there is a way the presence of certain paged ROMs might delay the interrupt processing? That might cause the behaviour to be consistent on a particular machine.
Also, it might be different on a Master.
Dave